The use of programmable phase-change materials (for example, materials which can be programmed between amorphous and crystalline states) for electronic memory applications is well known in the art and is disclosed, for example, in commonly assigned U.S. Pat. Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825,046 the disclosures of which are all incorporated by reference herein. Still another example of a phase-change memory element is provided in commonly assigned U.S. patent application Ser. No. 09/276,273, the disclosure of which is incorporated by reference herein.
Generally, phase-change materials are capable of being programmed between a first structural state where the material is generally amorphous and a second structural state where the material is generally crystalline. The term “amorphous”, as used herein, refers to a condition which is relatively structurally less ordered or more disordered than a single crystal. The term “crystalline”, as used herein, refers to a condition which is relatively structurally more ordered than amorphous. A phase-change material exhibits different electrical characteristics depending upon its state. For instance, in its crystalline, more ordered state the material exhibits a lower electrical resistivity than in its amorphous, less ordered state.
Materials that may be used as a phase-change material include alloys of the elements from group VI of the Periodic Table. These group VI elements are referred to as the chalcogen elements and include the elements Te and Se. Alloys that include one or more of the chalcogen elements are referred to as chalcogenide alloys. An example of a chalcogenide alloy is the alloy Ge2Sb2Te5.
FIG. 1 is an example of an programmable phase-change memory element. The memory element shown in FIG. 1 includes a substrate 2, a first contact 3 formed over the substrate 2, a chalcogenide phase-change material 5 formed over the first contact 3 and over dielectric 4, and a second contact 6 formed over the chalcogenide memory material 5. The memory element shown in FIG. 1 may be programmed between a plurality of resistance states by applying an appropriate current through the memory material. FIG. 2 is an example of a programmed plot of the resistance of a chalcogenide phase-change memory element versus the amplitude of a current pulse through the memory element. Referring to FIG. 2, several different programming regimes can be distinguished. In the left side of the curve, the resistance of the device remains substantially constant (i.e., in its high resistance or RESET state) until a current pulse of sufficient energy is applied. The device is then transformed from its high resistance (RESET) state to its low resistance (SET) state. A current pulse sufficient to program the memory element from the high resistance state to the low resistance state is referred to as a “set pulse”. While not wishing to be bound by theory, it is believed that the set pulse is sufficient to change at least a portion of the volume of memory material from a less-ordered amorphous state to a more-ordered crystalline state.
The memory device may be programmed back from the low resistance state or SET state to the high resistance or RESET state by applying a current pulse of sufficient amplitude, referred to as a “reset pulse”. While not wishing to be bound by theory, it is believed that application of a reset pulse to the memory element is sufficient to change at least a portion of the volume of memory material from a more-ordered crystalline state to a less-ordered amorphous state. The memory device may be programmed back and forth between the high resistance or RESET state and the low resistance or SET state. This type of programming scheme provides for a binary mode of operation (for example, the RESET state may be a logic 0 while the SET state may be a logic 1).
Referring to the right side of the curve of FIG. 2, as the amplitude of the current through the memory element increases, the resistance of the device increases. This increase is both gradual and reversible. In this regime, the phase-change memory element may be programmed to any resistance value within a window of resistance values bounded by the low resistance or SET state and the high resistance or RESET state. In this regime along the right side of the curve, the phase-change memory element may be programmed from any one of the resistance states on the right side of the resistance curve to any other of the resistance states on the right side of the curve by the application of a current pulse of sufficient amplitude. The device may thus be programmed between three or more resistance values within the resistance window so as to provide for multi-state, directly overwritable data storage. While not wishing to be bound by theory, it is believed that each of the resistance states along the right side of the curve may correspond to a particular ratio of the volume of crystalline material to the volume of amorphous material in an active region of the phase-change material. Three intermediate resistance states R1, R2 and R3 are shown in the resistance curve of FIG. 2.
In the example of the memory element shown in FIG. 1, the programming current is directed from one contact to another through the memory material. Hence, it is possible that relatively high current densities pass through the memory material causing electromigration within the body of chalcogenide and reducing the cycle life of the memory element. Hence, a new device structure is needed which will permit the memory element to be programmed without introducing electrical current into the chalcogenide material.